pci support

This commit is contained in:
rami 2024-08-01 14:22:25 -04:00
parent 113145e430
commit c60b008e94
9 changed files with 102 additions and 16 deletions

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@ -1,4 +1,4 @@
CC = /home/rami/crossdev/bin/i686-elf-gcc
CC = i686-elf-gcc
AS = nasm
BUILDDIR := build
@ -19,7 +19,7 @@ ISO := Hazel.iso
CFLAGS := -ffreestanding -Wall -Wextra -Werror -I $(INCLUDEDIR) -I lib
LDFLAGS := -ffreestanding -nostdlib -lgcc -T kernel/kernel.ld
QEMUFLAGS := -d int -cdrom $(BUILDDIR)/$(ISO) -s -m 512M -serial stdio
QEMUFLAGS := -cdrom $(BUILDDIR)/$(ISO) -s -m 512M -serial stdio
$(BUILDDIR)/$(KIMG): $(KOBJ) $(LOBJ)
$(CC) $^ -o $@ $(LDFLAGS)

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@ -44,7 +44,7 @@ struct GenericAddressStructure
uint64_t Address;
};
struct fadt {
typedef struct {
sdt_hdr_t hdr;
uint32_t FirmwareCtrl;
uint32_t Dsdt;
@ -109,10 +109,10 @@ struct fadt {
struct GenericAddressStructure X_PMTimerBlock;
struct GenericAddressStructure X_GPE0Block;
struct GenericAddressStructure X_GPE1Block;
};
} fadt_t;
rsdp_t *acpi_find_rsdp();
uint32_t acpi_checksum(void *s, int size);
void *acpi_find_sdt(rsdt_t *rsdt, const char sig[6]);
uint8_t acpi_checksum(void *s, int size);
void *acpi_find_sdt(rsdt_t *rsdt, const char *sig);
#endif

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@ -6,4 +6,10 @@
uint8_t inb(uint16_t port);
void outb(uint16_t port, uint8_t byte);
uint16_t inw(uint16_t port);
void outw(uint16_t port, uint16_t byte);
uint32_t inl(uint16_t port);
void outl(uint16_t port, uint32_t byte);
#endif

11
include/kernel/pci.h Normal file
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@ -0,0 +1,11 @@
#ifndef HAZEL_PCI_H_
#define HAZEL_PCI_H_
#include <stdint.h>
#define PCI_CONFIG_ADDR 0xCF8
#define PCI_CONFIG_DATA 0xCFC
uint16_t pci_read_cfg(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset);
#endif

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@ -16,24 +16,24 @@ rsdp_t *acpi_find_rsdp() {
return 0;
}
uint32_t acpi_checksum(void *s, int size) {
uint8_t acpi_checksum(void *s, int size) {
uint32_t sum = 0;
for (int i = 0; i < size; i++) {
sum += ((uint8_t *)s)[i];
}
return sum;
return (sum & 0xFF) == 0;
}
void *acpi_find_sdt(rsdt_t *rsdt, const char sig[6]) {
void *acpi_find_sdt(rsdt_t *rsdt, const char *sig) {
int entries = (rsdt->hdr.Length - sizeof(sdt_hdr_t)) / 4;
for (int i = 0; i < entries; i++) {
const char *ptr = (const char *)rsdt->other_tables[i];
int j = 0;
for (; j < RSDP_SIG_LEN; j++)
for (; j < 4; j++)
if (ptr[j] != sig[j]) break;
if (j == RSDP_SIG_LEN) return (void *)ptr;
if (j == 4) return (void *)ptr;
}
return 0;

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@ -15,3 +15,35 @@ void outb(uint16_t port, uint8_t byte) {
: // no output
: "a" (byte), "d" (port));
}
uint16_t inw(uint16_t port) {
uint16_t result;
asm volatile ("in %%dx, %%ax"
: "=a" (result)
: "d" (port));
return result;
}
void outw(uint16_t port, uint16_t byte) {
asm volatile ("out %%ax, %%dx"
: // no output
: "a" (byte), "d" (port));
}
uint32_t inl(uint16_t port) {
uint32_t result;
asm volatile ("in %%dx, %%eax"
: "=a" (result)
: "d" (port));
return result;
}
void outl(uint16_t port, uint32_t byte) {
asm volatile ("out %%eax, %%dx"
: // no output
: "a" (byte), "d" (port));
}

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@ -9,6 +9,7 @@
#include <kernel/task.h>
#include <kernel/ps2.h>
#include <kernel/acpi.h>
#include <kernel/pci.h>
#include <stdint.h>
kernel_ctx_t ctx = {0};
@ -126,16 +127,33 @@ void kernel(multiboot_info_t *info) {
rsdp_t *rsdp = acpi_find_rsdp();
if (!rsdp) goto halt;
if ((acpi_checksum(rsdp, sizeof(rsdp_t)) & 0xFF) != 0) goto halt;
LOG("RSDP found\n");
if (!acpi_checksum(rsdp, sizeof(rsdp_t))) goto halt;
if (rsdp->Revision == 0) LOG("Using ACPI version 1.0\n")
else if (rsdp->Revision == 2) {
LOG("ACPI versions higher than 1.0 are not currently supported!\n");
goto halt;
}
rsdt_t *rsdt = (rsdt_t *)(rsdp->RsdtAddress);
if (!rsdt) goto halt;
LOG("%08X\n", acpi_checksum(rsdt, rsdt->hdr.Length));
if (acpi_checksum(rsdt, sizeof(rsdt_t)) != 0) goto halt;
if (!acpi_checksum(rsdt, rsdt->hdr.Length)) goto halt;
LOG("RSDT is valid\n");
// for (;;) {}
void *mcfg = acpi_find_sdt(rsdt, "MCFG");
if (!mcfg) LOG("PCIe not supported\n");
for (int i = 0; i < 256; i++) {
for (int j = 0; j < 32; j++) {
for (int k = 0; k < 8; k++) {
uint16_t w = pci_read_cfg(i, j, k, 0xA);
uint8_t class = (uint8_t)(w >> 8);
uint8_t subclass = (uint8_t)w;
if (class == 0xFF) continue;
LOG("Class: %04X | Subclass: %04X\n", class, subclass);
}
}
}
pic_remap(PIC_1_START, PIC_2_START);
ps2_init();

19
kernel/pci.c Normal file
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@ -0,0 +1,19 @@
#include <kernel/pci.h>
#include <kernel/io.h>
uint16_t pci_read_cfg(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset) {
uint32_t address;
uint32_t lbus = (uint32_t)bus;
uint32_t lslot = (uint32_t)slot;
uint32_t lfunc = (uint32_t)func;
uint16_t tmp = 0;
// Create configuration address as per Figure 1
address = (uint32_t)((lbus << 16) | (lslot << 11) |
(lfunc << 8) | (offset & 0xFC) | ((uint32_t)0x80000000));
outl(PCI_CONFIG_ADDR, address);
tmp = (uint16_t)((inl(PCI_CONFIG_DATA) >> ((offset & 2) * 8)) & 0xFFFF);
return tmp;
}